Optical recording disk capable of resynchronization in digital encoding and decoding

ABSTRACT

In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

This is a divisional of U.S. application Ser. No. 08/212,724, filed onMar. 14, 1994, and now is U.S. Pat. No. 5,546,427.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of Ser. No. 09/295,376, filed Apr. 21,1999, which is a reissue of Ser. No. 08/592,486, filed Jan. 26, 1996(U.S. Pat. No. 5,623,477 ) which is a division of Ser. No. 08/212,724,filed Mar. 14, 1994 (U.S. Pat. No. 5,546,427 ), and which is beingincorporated herein by reference.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,623,477. The reissue applications are a parentreissue application Ser. No. 09/295,376 and three divisional reissueapplications, namely Ser. No. 10/138,738 (the present application) ,Ser. Nos. 10/137,488 and 10/138,737.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a recording/reproducing apparatus whichrecords and reproduces digital signals, and more particularly to thedigital data encoding/decoding apparatus for optical disk apparatuswhich carries out mark edge recording by pit width modulation.

2. Related Art of the Invention

In recent years, the optical disk apparatus has attracted keen publicattention as a digital information recording/reproducing apparatus witha large storage capacity and the ability to interchange media. In theoptical disk apparatus, the digital data is encoded for recording insuch a manner that it fits in the recording/reproducing channelcharacteristics determined by the optical head and optical recordingmedia, and reproduced signals are data-detected to make binary-codedsignals, from which decoding is carried out to obtain original digitaldata. Based on this, encoding and decoding techniques to enableefficient digital recording and reproducing have been put into practicaluse as various digital data encoding/decoding apparatus.

In the general procedure to record and reproduce digital data, first ofall, the code stream obtained by encoding the data with modulationhaving a proper rule is recorded. When reproducing, the clock signalswhich are clock components of the code stream are retrieved from thereproduced signals by utilizing the properties of the code streamimparted by the above-mentioned modulation. Based on the retrieved clocksignals obtained, the recorded code stream is separated and the originaldigital data is obtained by decoding, which is the operation reverse toencoding. As one example, in the standard format of a 130-mm-diametermagneto-optic disk data file apparatus, a (2, 7) code is used as theencoding system as found in the International Standard (ISO/IEC DIS10089). Table 1 shows the conversion rule of the (2, 7) code.

The (2, 7) code is an encoding system which converts 1-bit digital datato 2-bit codes, and is so called because of its characteristics that a“1” is separated by a minimum of two “0's” and a maximum of seven “0's”in the code stream after encoding an original digital data stream. Thisencoding rule is called (d, k) conversion rule because a “1” isseparated by a minimum of d “0's” and a maximum of k “0's” in the codestream after encoding. Consequently, in the case of the (2, 7) code, a“1” exists intermittently at the clock frequency from 3 to 8 in the codestream after encoding, and with this point as a premise, the codefrequency which is a clock component is obtained to make a reproducedclock signal, rendering itself capable for detecting the above-mentioneddata.

In general, in this type of encoding/decoding, decoding timing to thebits of the code stream and the data stream is to be properly providedwhen the original data stream is decoded from the reproduced codestream. Otherwise, such decoding timing failure does not keep the ruleof the encoding system and will result in errors. In the case of Table1, the 1-bit data must be made to correctly correspond with the 2-bitcode. For this purpose, a specific code pattern called SYNC or RESYNCBYTE is inserted in the code stream after encoding to achieve bitsynchronization at the time of decoding. In the above-mentionedinternational standard, for the RESYNC BYTE,{0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0}is periodically inserted, and in the event of decoding operation, first,this RESYNC BYTE is detected; then, based on this, the above-mentionedbit synchronization is achieved for decoding. This RESYNC BYTE is apattern which cannot exist in any code stream after encoding for anydata stream in the rule specified in Table 1, and a RESYNC BYTE willnever be detected by mistake with other code data.

This kind of method enables this bit synchronization by periodicallyarranging bit patterns, which can easily be identified, as a RESYNC BYTEto achieve bit synchronization in the encoded code streams as describedin, for example, OPTICAL DATA FORMAT EMPLOYING RESYNCHRONIZABLE DATASECTORS, U.S. Pat. No. 4,791,622 by D. W. Clay et al. and SYNC ENCODINGSYSTEM FOR DATA SECTORS WRITTEN ON A STORAGE MEDIUM, U.S. Pat. No.4,797,167 by M. J. O'Keeffe et al. This bit synchronization pattern iscalled a SYNC BYTE when it is used at the data head, and a RESYNC BYTEwhen used at the intermediate position. The SYNC BYTE decides the bitsynchronization at the start of decoding, while the RESYNC BYTEperiodically corrects deviation of a decoding bit to prevent propagationof decoding error after any defect occurs when clock reproductionfailure occurs in the middle of data reproduction, and both frequentlyhave the same patterns.

In the meantime, in the present optical disks, a large number ofdevelopments have been undertaken to increase the capacity to store moreand more information, and in order to avoid complication of datacontrols associated with the increased storage capacity, the unit of therecording data amount must also be increased. When the recording dataunit is increased, there will be more possibility to cause failure toreproduce clocks during data reproduction due to the drop-out ofreproduced signals arising from a defect of the media, and the systemreliability will be lowered. The importance of the RESYNC BYTE has beenfurther increased to suppress continuous occurrence of decoding errorsin order to prevent disability in decoding all of the data after theclock reproduction failure occurs.

In the conventional optical disk apparatus, as a method to record andreproduce data, mark position recording (MPR) in which the recordingmark position is used for information recording is carried out; this iscalled pit position modulation (PPM) because of the recording pit,another name of the recording mark, and has characteristics to correctlyrecord and reproduce the data even when there is a variation in pitsize. However, in order to further increase the recording density, thepit width modulation (PWM) which carries out mark edge recording (MER),in which the position and length of the recording mark are used forrecording of information, has begun to be put into practical use.

For the encoding rule in the PPM recording system, the(2, 7) code hasthe superior capabilities, and the PPM recording system using this (2,7) code has been adopted in the above-mentioned international standard,but as part of further improving the recording density, in the PWMrecording, investigation has been made on systems such as a (1, 7) code.In this mark edge recording, NRZI code is performed after a (2, 7) or(1, 7) code. The positional relationship between the mark formed incorrespondence with the part in which “1” of the code stream obtained asabove continues and the space other than this formed by “0” is used forrecording information.

The mark is formed by applying the comparatively high optical output tothe medium and locally raising medium temperature, and has a problemthat the positional relationship of mark edge deviates when the opticaloutput deviates from the optimum value. That is, when the optical outputis greater than the optimum value, the recorded mark generally becomeslarger, and, on the contrary, when it is smaller, it becomes smaller,causing the power margin, the set margin for optical output inrecording, to become smaller. In this way, the positional relationshipbetween the mark initiation end and the finish end deviates from theoptimum bit intervals of code data, resulting in higher possibility tocause decoding errors in achieving synchronization of data fromreproduced signals for decoding.

When the (2, 7) code is used as a technique to solve this kind ofproblem, for example, as is found in DATA RECORDING/REPRODUCING DEVICE,U.S. Pat. No. 5,229,986 by Mizokami et al., specifically designing thedata detection method during reproduction has enabled the development ofa technique to improve the detection allowance for mark formation. Inthis method, synthesis of both takes place after the mark initiation endand the finish end are independently binary-coded and clock-reproduced,and both are designed to achieve bit-synchronization independently.Consequently, the data detection method is limited and it is notgenerally applicable.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a highly reliableapparatus with improved recording/reproducing power margin, etc. byrealizing highly reliable RESYNC BYTEs in optical disks using mark edgerecording.

It is another object of the present invention to provide an apparatuswhich can detect RESYNC BYTES satisfactorily in an optical disk of theCLV (constant linear velocity) system.

Furthermore, it is another object of the present invention to detectgood RESYNC BYTES eve in an optical disk with different erasecharacteristics for the mark and space by limiting the RESYNC detectionpart of RESYNC BYTES to the mark or space.

Preferably, a specific pattern is given to the invalid data of theportion corresponding to RESYNC BYTES to operate an encoder, and ininserting RESYNC BYTES in the corresponding portion of the code streamafter encoding, the present invention enables smooth connection in termsof code regularity.

The above and other objects of the present invention are realized in thedigital data encoding apparatus of the present invention thatperiodically inserts RESYNC BYTES comprising a bit compensation part,RESYNC detection part, and bit synchronization part into the code streamof the digital data encoded in accordance with the (d, k) conversionrule.

In addition, the digital data encoding method and apparatus of thepresent invention has an encoding means to encode data input inaccordance with the (d, k) conversion rule and RESYNC BYTES adding meanswhich periodically generates RESYNC BYTES comprising a bit compensationpart, RESYNC detection parts, and a synchronization part. Furthermore,it is provided with an encoding means to perform NRZI encoding on the(d, k) encoded code and RESYNC BYTES.

The digital data decoding apparatus of the present invention comprises ameans to detect RESYNC BYTES, a means to detect bit synchronization, anda decoding means to be initialized by the means to detect bitsynchronization.

In addition, by making the RESYNC detection part longer than k, thecorrelationship between RESYNC BYTES and code data of other parts ismade extremely small.

Furthermore, by making the size of RESYNC detection part sufficientlylarger than k, exclusive detection of RESYNC BYTES is made easy even inthe CLV system.

The present invention will achieve highly reliable decoding operation byrealizing RESYNC BYTE comprising a bit compensation part, RESYNCdetection part, and bit synchronization part and initializing thedecoder by detecting the bit synchronization part after detecting theexistence of the RESYNC detection part based on the above-mentionedconfiguration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of the recording format;

FIG. 2 is a block diagram illustrating a digital encoding apparatus inone embodiment of the present invention;

FIG. 3 is signal waveform illustrating the operation of FIG. 2;

FIG. 4 is a block diagram illustrating the digital decoding apparatus inone embodiment of the present invention;

FIG. 5 is signal waveform illustrating the operation of FIG. 4;

FIG. 6 is signal waveform illustrating the operation of FIG. 2;

FIG. 7 is a block diagram illustrating the digital encoding apparatus inanother embodiment of the present invention;

TABLE 1 is a conversion table of (2, 7) code;

TABLE 2 is a conversion table of (1, 7) code;

TABLE 3 is No. 1 table of RESYNC BYTES;

TABLE 4 is No. 2 table of RESYNC BYTES.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings, a digital data encoding method andapparatus of one embodiment according to the present invention isdescribed with the case taken as an example, in which audio signal 2channels and video signals are recorded and reproduced by the digitaldata.

Digital data is recorded and reproduced along the recording track formedon the optical disk medium and for recording and reproducing units,sectors are set in such a manner to divide the one-round recording trackas shown in the track format of FIG. 1. Each sector consists of addressID (ADRS) set at the head which shows the pre-formatted sector address,audio data 0, audio data 1, and video data are arranged on the diskmedium with gaps in-between. The disk rotating speed is constant and theaudio data and video data recording and reproducing timing is controlledwith the address ID detection timing set as a standard. Every time thedisk medium is exchanged, the disk center deviates by about scores ofmicrometers, and the timing of data deviates due to this centerdeviation. However, the above-mentioned gaps are provided with thisdeviation taken into account to prevent any trouble from occurring inrecording and reproduction.

The video data part begins with a VFO (variable frequency oscillator),which is a fixed continuous pattern for synchronizing clockreproduction, and comprises an 8-byte-long pre-amble block which beginswith SYNC (synchronization) BYTES, a continuation of a 94-byte-longblock beginning from RESYNC (resynchronization) BYTES, and finally4-byte-long post-amble block including RESYNC BYTES. The SYNC BYTES andRESYNC BYTES are used to achieve data synchronization when reproducedsignals are decoded, and SYNC BYTES and RESYNC BYTES are designed tohave the same patterns.

This format is a recording format of a ZCAV (zone-divided constantangular velocity) system with a storage capacity increased by dividingthe recording tracks in a plurality of zones in accordance with the sizeof the disk radius and varying the number of blocks beginning from theabove-mentioned RESYNC BYTES in accordance with the zone, and the numberof blocks is varied from 106 to 200 in accordance with the disk radiusposition of the track.

Now, the roles of the digital data encoding apparatus are to encode thedata into a data stream formatted as shown in FIG. 1, and, then, toinsert SYNC BYTES or RESYNC BYTES. The roles of the digital datadecoding apparatus are to detect SYNC BYTES or RESYNC BYTES from thedata detected from the reproduced signals, and based on the detectionresults, to decode the data while achieving proper bit synchronizationof the decoder and to obtain the original recorded data.

A (1, 7) code is used for encoding. Table 2 shows the conversion tableof the (1, 7) code.

In Table 2, a 3-bit code is assigned for 2-bit data before encoding, andas an exception, a 6-bit code is assigned to the 4-bit data list in thetable. As a result, for any size of data list, in the encoded code list,a “1” is separated by a minimum of one “0” and a maximum of seven “0's.”At the time of decoding, conversely, 2-bit or 4-bit data is assigned to3-bit or 6-bit code, and therefore, it is necessary to achievesynchronization in units of 2-bit data to 3-bit code.

FIG. 2 shows a configuration of a digital data encoding apparatus in oneembodiment according to the present invention, while FIG. 3 illustratesthe signal waveform to describe the operation.

In FIG. 2, numeral 1 denotes that (1, 7) encode, 2 the NRZI encoder, 3an exclusive OR gate, 4 an AND gate, 5 D-type flip flop, 6 a patterndetector, 7 a fixed part register, 8 a RESYNC generator, 9 a switch, and10 a timing controller. The RESYNC generator 8 and switch 9 compose aRESYNC adding means. Now referring to FIG. 2 and FIG. 3, operation ofthe digital data encoding apparatus configured as above is described.

In FIG. 1, the digital data are formatted as VFO-RESYNC BYTES,post-amble, etc. are arranged, and added to the (1, 7) RLL encoder 1.The (1, 7) RLL encoder 1 converts the data in accordance with theconversion table shown in Table 2 and outputs. For example, in theformatted data corresponding to VFO, a value consisting of allcontinuous “0” is fixedly given, and as clear from Table 2, in theencoder output, a signal “010” pattern continues. This single pattern isused for pull-in of PLL which carries out clock reproduction at the timeof reproduction. The data corresponding to RESYNC BYTES is 2 bytes longand has 16 consecutive “0's” arranged in advance, and the RESYNC BYTESinserted after encoding are 24 bits.

Now, RESYNC BYTES comprise a bit compensation part (BCP) which is {Ca Ca0 0 0} (Ca=0, 1), a RESYNC detection part (BDP) consisting of 11consecutive “1” {1 1 1 1 1 1 1 1 1 1 1}, and a bit-synchronization part(BSP) of {0 0 0 1 1 1 0 0}, and is expressed as{Ca Ca 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0}  (1)

FIG. 3 (a) shows the data in the vicinity including this RESYNC BYTE,and the data (b) encoded by the (1, 7) RLL encoder 1 is further encodedwith the NRZI encoder comprising the exclusive OR gate 3, AND gate 4,and D-type flip flop 5. In this event, adding the RESYNC positioningsignal (c) given by the timing controller 10 to the AND gate 4initializes the NRZI encoder 2 for every RESYNC BTYE position. Thisinitialization causes the NRZI encoder 2 output to be (d) and the NRZIencoder 2 output at the position right after RESYNC BYTE is fixed to“0.” In addition, the pattern decoder 6 is controlled by the timingcontroller 10, monitors the patterns of NRZI encoder 2 output, andoutputs No. 1 and No. 2 bits of the bit compensation part as {1, 1} or{0, 0} in accordance with the patterns right before the RESYNC BYTE. Inthe example of FIG. 3, {1 1} is outputted. The code patterns rightbefore the RESYNC BYTE after NRZI encoding are classified as shown inTable 3 with all the combinations shown in Table 2 taken into account.Following this, the fixed part register 7 outputs {0 0 0 1 1 1 1 1 1 1 11 1 1 0 0 0 1 1 1 0 0}. In this event, the code data inserted as RESYNCBYTE is (1) and Ca=1.{1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0}

The switch 9 inserts the output of the RESYNC generator 8, whichcomprises the pattern detector 6 and fixed part register 7, to the NRZIencoder 2 by the RESYNC BYTE timing given by the timing controller 10.Consequently, the output of switch 9 becomes as shown with (e) and therecorded data are recorded and the recorded mark is formed as per (f).

With a series of operations as above, the recorded data becomes the (1,7)-encoded and NRZI-encoded code stream with RESYNC BYTES periodicallyinserted. The bit compensation part in RESYNC BYTES operates to enablethe (1, 7) encoding rule to be smoothly connected to the RESYNCdetection part in inserting RESYNC BYTES, and RESYNC BYTES areconfigured to enable the RESYNC detection part to have 11 consecutive“1's,” and the bit synchronization part has an isolated {1 1 1} patternseparated by “0's”.

In the above configuration and operation, the RESYNC detection part isdesigned to fixedly have 11 consecutive “1's” but if it is not fixed to“1” and may be a continuation of either “1's” or “0's,” initializationof the NRZI encoder 2 is not needed and the circuit can be simplified.The RESYNC BYTE in this case is expressed as follows in which the RESYNCBYTE should be that before NRZI encoding is performed in the case of(1), and {Cb 0 Cc 0 0 0} (Cb, Cc=0, 1) is assigned to the bitcompensation part, {1 0 0 0 0 0 0 0 0 0 0} to the RESYNC detection part,and {1 0 0 1 0 0 1 0} to the bit synchronization part{Cb 0 Cc 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0}  (2).This means that after this RESYNC BYTE is inserted into the (1, 7)encoded data, NRZI encoding is performed. That is, the pattern detectionpart monitors the data right before RESYNC BYTES of the data stream (1,7) encoded as per (b) of FIG. 3 and outputs No. 1 to No. 3 bits amongthe bit compensation part {Cb 0 Ca 0 0} given by Table 4, while thefixed part register outputs the remaining 2 bits {0 0} of the bitcompensation part, {1 0 0 0 0 0 0 0 0 0 0} of the RESYNC detection part,and {1 0 0 1 0 0 1 0} of the bit synchronized part.

After this RESYNC BYTE is inserted into a proper position by a switch,NRZI encoding takes place. Consequently, the RESYNC BYTE part has thefollowing two cases in the RESYNC detection part: one in which “0”continues and the other in which “1” continues:{X X 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1} X=0, 1or{X X 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0} X=0, 1

In addition, RESYNC BYTES of (1) and (2) are 2 bytes in data lengthbefore encoding but to achieve resynchronization, still shorterconfiguration is possible. For example, in the example of RESYNC BYTESof 1.5 bytes long which corresponds to (2), the bit compensation part isassigned to {Cb 0} (Cb=0, 1), RESYNC detection part to {1 0 0 0 0 0 0 00 0 0}, and bit synchronization part to {1 0 0 1 0}; then, it ispossible to use RESYNC BYTES of{Cb 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0}  (3)

FIG. 4 is an embodiment of the digital data decoding apparatusaccording, to the present invention, which corresponds to the digitaldata encoding apparatus of FIG. 2. FIG. 5 shows the waveform to describethe operation. In FIG. 4, numeral 11 is an exclusive OR gate, 12 aD-type flip flop, 13 a NRZI decoder, 14 a (1, 7) decoder, 15 a patterndetector, 16 a bit synchronization detector, 17 a timing generator, and18 a RESYNC detector comprising 15, 16 and 17.

The reproduced signal obtained by reproducing the recorded mark (b)formed by recording the recorded data shown in FIG. 5 (a) is the signalas shown in (c), in which the recorded data is low-pass-filtered. Thisreproduced signal is data-detected and the recorded code stream isobtained. In data detection, first of all, a suitable slice level isprovided for the reproduced signal and is made into the binary-codedsignal by a compensator as shown in (d). From this binary-coded signal,the reproduced clock signal CLOCK1 of (e), the clock component, isreproduced by the phase locked loop, and based on this reproduced clocksignal, the recorded code data is detected as shown in (f).

The obtained signal (f) is inputted into FIG. 4. The pattern detector 15detects the generation of the RESYNC detection part as shown in (g). Inthis detection, because in the code stream outside the RESYNC BYTES, amaximum 8 “1's” are allowed continue based on the (1, 7) conversionrule, it is assumed that there would be no mis-detection of the RESYNCdetection part. The bit synchronization detector 16 detects “0 1 1 1 0”and outputs as shown in (i). The timing generator 17 uses outputs of thepattern detector 15 and bit synchronization detector 16 as its inputs,and outputs RESYNC detection signal (j) as well as signal CLOCK2corresponding to the clock of decoded data, which is (1, 7) encoded,when the RESYNC detection part of RESYNC BYTES and then the bitsynchronization part can be detected while the RESYNC gate signal ofFIG. 5 (h) is enabled, and in addition, from the RESYNC BYTE cycledefined by the recording format, the timing generator 17 generates theabove-mentioned RESYNC gate signal. The NRZI decoder 13 NRZI-decodes theinput code stream and outputs as shown in (k). The (1, 7) decoder 14decodes the data in accordance with the inverse conversion rule shown inTable 2 from the decoded clock CLOCK2 in good bit synchronizationoutputted by the timing generator 17 and outputs as shown in (1). Atthis point, in (1, 7) decoding, because the RESYNC detector is the datawhich does not satisfy the conversion rule, it always generates an errorresulting in demodulation failure at the portion corresponding to RESYNCBYTES, but because of the characteristics of the conversion rule shownin Table 2, this error does not propagate beyond the RESYNC BYTES andthe RESYNC detector recovers normal decoding condition.

In the manner as described above, RESYNC BYTES are detected and correctdecoding takes place.

In a series of operations as above, the mark formed as the RESYNCdetector is comparatively longer than that of other data portions, andthe peak shift, etc. generated by recording and reproduction is likelyto increase. For this reason, the RESYNC detector tends to arrange bymistake 10 or 12 consecutive “1's.” Considering such cases, it isallowed to assign all of 10, 11, and 12 consecutive “1's” in the codestream to the RESYNC detector as a detection standard of the patterndetector 15. The 10,11, and 12 are examples of the k+2 to k+4. On theother hand, in the (1, 7) encoded data portion outside the RESYNC BYTES,the number of continuing “1's” is a maximum of 8, and even when thisbecomes nine consecutive “1's” by mistake due to the peak shift, this isnot mistakenly taken as the RESYNC detector.

More generally, for the modulation expressed by the (d, k) conversionrule, the continuous length of “1's” at the RESYNC detector is assignedto k+3 and its detection standard is designated as k+2, k+3, or k+4.This same principle is applied to the case in which RESYNC BYTES of (2)are established to simplify the apparatus.

In addition as shown in FIG. 2, when the RESYNC detector is fixed toallow “1's” to continue, there are following advantages.

In the re-writable type optical disks, after erasing the data previouslyrecorded, recording is carried out newly or recording is carried outsimultaneously with erasing (direct overwrite) but there is a problemthat the recording condition before overwriting remains unerased. Inparticular, in the phase change recording medium which records andreproduces information by the use of the change of reflectivity, thelonger the space part, the more serious is the unerased problem, becausethe previously recorded mark remains unerased, which should have beenerased during overwriting. In PPM recording, for example, as describedin “Overwrite Characteristics in Phase Change Optical Disk” by Ishida etal. (Proc. of Int. Symp. on Optical Memory, 1989), the unerased area inthe vicinity of the recorded mark is comparatively small and the problemof the unerased area is minor. However, in the PWM recording whichutilizes all of the mark and space positional information, the problemof the unerased area is critical. It is known that this kind of unerasedarea problem is scarcely generated for the mark and significantlygenerated at the space portion only. In the above-mentioned RESYNC BYTE(2), if the RESYNC detector has consecutive “0's” the unerased area ofthe RESYNC detector as shown in FIG. 4 (a) causes a problem, producingthe reproduced signal as shown in (b) at this portion. Consequently, inthe binary-coded signal (c), RESYNC detection is disabled. However, whenthe RESYNC detector is fixed to “1” such as RESYNC BYTES (1), theeffects of unerased mark area are small and even if the same level ofthe erased area exists, RESYNC detection is not disabled.

Meanwhile as shown in FIG. 7, the NRZI encoding operation can beexecuted after the RESYNC BITE adding operation.

As described above, the present invention contemplates to provide anexcellent method and apparatus for digital data encoding/decoding whichenables resynchronization without mistakenly detecting code data ofother portions as RESYNC codes by arranging the RESYNC BYTES comprisinga bit compensation part, RESYNC detection part, and a bitsynchronization part in the code data after modulation, detecting theexistence of RESYNC BYTES by detecting the RESYNC detection part, andfurther detection the bit synchronization part to achieve bitresynchronization.

In particular, for the (1, 7) conversion rule in Table 2, the value ofthe digital data corresponding to the synchronization code can all beencoded to “0's” in advance and the code data corresponding to the bitsynchronization part before they are replaced to RESYNC BYTES can bemade identical to those after replacement, enabling the replacement bysimple switching and providing features that the hardware can besimplified. In addition, decoding of the code data part following theRESYNC BYTES can be continuously carried out without any hindrance,enabling the easy initialization of the decoder by detection of the bitsynchronization part. A bit compensation part is provided before theRESYNC detection part, thereby achieving smooth connection between thecode data and RESYNC BYTES, and the clock of the phase locked loop isreproduced without any trouble. In addition, by limiting the RESYNCdetection part to the mark, mis-detection for RESYNC BYTES by theunerased area can be reduced.

In addition, in the present invention, by taking a sufficiently longRESYNC detection part, the correlationship between the data part and theRESYNC BYTES is made smaller, and RESYNC BYTE detection free frommisdetection is achieved. If this feature is utilized, even in the CLV(constant linear velocity) system, a format adopted to compact disks,etc., it is apparent that the problem that the deviation of linearvelocity of the recording track becomes greater than a specified levelcan be solved and satisfactory RESYNC detection is readily available.

TABLE 1 DATA CODE 10 0100 010 100100 0010 00100100 11 1000 011 0010000011 00001000 000 000100

TABLE 2 DATA CODE 11 101 10 100 01 001 00 010 1111 101000 1110 1000000111 001000 0110 010000

TABLE 3 right before bit substituted code array code compensation BCPRDP BSP ←A→ part Ca ←A→ ←—→ ←—→ ←—→ XXXXX01 11000 0 XXXXX01 1100011111111111 00011100 XXXXX10 00000 0 XXXXX10 00000 11111111111 00011100XXXX011 11000 1 XXXX011 11000 11111111111 00011100 XXXX100 00000 1XXXX100 00000 11111111111 00011100 XXX0111 11000 1 XXX0111 1100011111111111 00011100 XXX1000 11000 1 XXX1000 11000 11111111111 00011100XX01111 00000 0 XX01111 00000 11111111111 00011100 XX10000 11000 0XX10000 11000 11111111111 00011100 X011111 00000 1 X011111 0000011111111111 00011100 X100000 11000 1 X100000 11000 11111111111 000111000111111 00000 1 0111111 00000 11111111111 00011100 1000000 11000 11000000 11000 11111111111 00011100

TABLE 3 right before bit substituted code array code compensation BCPRDP BSP ←A→ part Aa Ab ←A→ ←—→ ←—→ ←—→ XXXXX01 00100 0 1 XXXXX01 0010010000000000 10010010 XXXX010 00100 0 1 XXXX010 00100 1000000000010010010 XXX0100 10000 1 0 XXX0100 10000 10000000000 10010010 XX0100010000 1 0 XX01000 10000 10000000000 10010010 X010000 10000 1 0 X01000010000 10000000000 10010010 0100000 10000 1 0 0100000 10000 1000000000010010010

1. An optical disk having a recording surface including first regionsthat represent first data and second regions that represent second data;the first regions and the second regions together representing digitaldata carried by said disk and RESYNC BYTES present at a certain intervalbetween groups of digital data on said disk; the first regions and thesecond regions each having areas that represent the digital data asdigital data that is encoded to satisfy a (d,k) conversion rule whereind is a minimum number of first data and k is a maximum number of firstdata that separate a datum of the second data, and that represent theRESYNC BYTES as bytes that each include a RESYNC detection part thatviolates the (d,k) conversion rule, and a bit synchronization part thatsatisfies the (d,k) conversion rule.
 2. An optical disk as claimed inclaim 1, wherein the first regions include pits in the recording surfaceand the second regions do not include pits in the recording surface. 3.An optical disk as claimed in claim 2, wherein one of the first data andthe second data is a logical “0” and the other of the first data and thesecond data is a logical “1”; wherein the representing areas of thefirst regions and the second regions further represent the RESYNC BYTESas BYTES that each include a bit compensation part located at a headposition in the RESYNC BYTE, wherein the RESYNC detection part has anumber N, of “0's” which separate “1's” that is N>k, and wherein the bitsynchronization part consists of at least a minimum of one “0” and aminimum of one “1”.
 4. An optical disk as claimed in claim 3, wherein a“1” is separated by k+3 “0s” in the RESYNC detection part.
 5. An opticaldisk as claimed in claim 2, wherein the areas of the first regions andthe second regions represent the (d, k) encoded digital data and theRESYNC BYTES also as an NRZI encoded data stream.
 6. An optical disk forstoring data, comprising: a recording surface including first regionsfor representing digital data that satisfy a (d, k) conversion rule andsecond regions for representing RESYNC BYTE data including RESYNC BYTES,said second regions being periodically inserted in said first regions,wherein each of said RESYNC BYTES incldues a RESYNC detection part thatviolates said (d, k) conversion rule, a bit synchronization part thatsatisfies said (d, k) conversion rule, and a bit compensation partlocated at a head position of each said RESYNC BYTE, said digital dataand the RESYNC BYTE data are comprised of first type data and secondtype data, and d and k of said (d, k) conversion rule respectivelyindicate a minimum number and a maximum number of said first type databetween two data of said second type data.
 7. A digital coding methodfor recording data on an optical disk, said method comprising the stepsof: modulating digital data encoded in accordance with a (d, k)conversion rule for providing modulated data; and adding RESYNC BYTEdata including RESYNC BYTES in said modulated data, each of said RESYNCBYTES having a RESYNC detection part which violates said (d, k)conversion rule, a bit synchronization part which satisfies said (d, k)conversion rule, and a bit compensation part located at a head positionof each said RESYNC BYTE, said digital data and said RESYNC BYTE databeing comprised of first type data and second type data, and d and k ofsaid (d, k) conversion rule respectively indicating a minimum number anda maximum number of said first type data between two data of said secondtype data.